Patents | yung-hsien-wu

─── PATENTS ───

Cheng-Chieh Lai, Meng-Ting Yu, Yung-Hsien Wu, Kuang-Hsin Chen, “Capacitor Embedded with Nanocrystals,” US Patent, US 10930583, Date of Patent Grant: 2021/02/23. (Invention derived from a collaborative project between TSMC and NTHU led by me)
I-Chen Huang, Yi-Ju Hsu, Kuang-Hsin Chen, Chi-Wen Liu, Yung-Hsien Wu, Chin-Yu Chen, “Manufacture Method, High K Dielectric Structure and its Manufacture Method of Semiconductor Devices,” China Patent, CN 107316809, Date of Patent Grant: 2021/03/16. (Invention derived from a collaborative project between TSMC and NTHU led by me)
Cheng-Chieh Lai, Meng-Ting Yu, Yung-Hsien Wu, Kuang-Hsin Chen, “Capacitor Embedded with Nanocrystals,” US Patent, US 10319675, Date of Patent Grant: 2019/06/11 (Invention derived from a collaborative project between TSMC and NTHU led by me)
I-Chen Huang, Kuang-Hsin Chen, Yung-Hsien Wu, Wen-Chao Shen, “Semiconductor Device Structure,” US Patent, US 10163516, Date of Patent Grant: 2018/12/25. (Invention derived from a collaborative project between TSMC and NTHU led by me)
I-Chen Huang, Yi-Ju Hsu, Chi-Wen Liu, Kuang-Hsin Chen, Yung-Hsien Wu, Chin-Yu Chen, “Method of Manufacturing High-K Dielectric Using Hfo/Ti/Hfo Layers,”US Patent, US 10068984, Date of Patent Grant: 2018/09/04. (Invention derived from a collaborative project between TSMC and NTHU led by me)
Cheng-Chieh Lai, Kuang-Hsin Chen, Shih-Kai Fan, Yung-Hsien Wu, Yu-Hsun Chen, “Semiconductor Component and Method for Fabricating the Same,” US Patent, US 10008494, Date of Patent Grant: 2018/06/26. (Invention derived from a collaborative project between TSMC and NTHU led by me)
I-Chen Huang, Yi-Ju Hsu, Kuang-Hsin Chen, Chi-Wen Liu, Yung-Hsien Wu, Chin-Yu Chen, “半導體裝置的製造方法、高介電常數介電結構及其製造方法,” Taiwan Patent, TW I619176, Date of Patent Grant: 2018/03/21. (Invention derived from a collaborative project between TSMC and NTHU led by me)
Cheng-Chieh Lai, Meng-Ting Yu, Yung-Hsien Wu, Kuang-Hsin Chen, “半導體結構與其形成方法,” Taiwan Patent, TW I611551, Date of Patent Grant: 2018/01/11. (Invention derived from a collaborative project between TSMC and NTHU led by me)
Cheng-Chieh Lai, Kuang-Hsin Chen, Shih-Kai Fan, Yung-Hsien Wu, Yu-Hsun Chen, “Semiconductor Component and Method for Fabricating The Same,” Korea Patent, KR 101777020, 2017/09/08. (韓國專利獲證，本人主導之發明，台積電產學合作衍生專利)
賴政杰, 范士凱, 陳光鑫, 巫勇贤, 陳昱勳, “半導體組件及製造其之方法,” Taiwan Patent, I588993, 2017/06/21. (台灣專利獲證，本人主導之發明，台積電產學合作衍生專利)
I-Chen Huang, Kuang-Hsin Chen, Yung-Hsien Wu, Wen-Chao Shen, “Semiconductor Device Structure,” US Patent, US 9673340, 2017/06/06. (美國專利獲證，本人主導之發明，台積電產學合作衍生專利)
Cheng-Chieh Lai, Kuang-Hsin Chen, Shih-Kai Fan, Yung-Hsien Wu, Yu-Hsun Chen, “Semiconductor Component and Method for Fabricating The Same,” US Patent, US 9570568, 2017/02/14. (美國專利獲證，本人主導之發明，台積電產學合作衍生專利)
Yung-Hsien Wu, Min-Lin Wu “單次寫入多次讀取記憶體及其製造方法,” Taiwan Patent, TW I469266, Date of Patent Grant: 2015/01/11.
巫勇賢, 王立康, 荊鳳德, “選擇性射極太陽電池的製程” Taiwan patent I 449198, 2014/08/11.
Yung-Hsien Wu, Li-karn Wang and Feng-Der Chin, “Process for Selective Emitter Solar Cell,” U. S. patent, 8288193, 2012/10/16.
Yung-Hsien Wu, Li-Karn Wang, Feng-Der Chin, “Manufacture Procedure of Selective Emitter Solar Battery” China Patent, CN 102054898B, Date of Patent Grant: 2012/10/31.
Yung-Hsien Wu, “非揮發性記憶體之製造方法,” Taiwan Patent, TW I280668, Date of Patent Grant: 2007/05/01.
Yung-Hsien Wu, “DRAM and Manufacturing Method Thereof,” China Patent, CN 1770427, Date of Patent Grant: 2007/11/21.
Yung-Hsien Wu, “Non-Volatile Memory Manufacturing Method,” China Patent, CN 1767174, Date of Patent Grant: 2007/12/12.
Yung-Hsien Wu, Hwei-Lin Chuang, “電容介電層結構及其製造方法,” Taiwan Patent, TW I254448, Date of Patent Grant: 2006/05/01.
Yung-Hsien Wu and Cheng-Che Lee, “Capacitor Dielectric Structure of a DRAM Cell and Method for Forming Thereof,” US Patent, US 7030441, Date of Patent Grant: 2006/04/18.
Yung-Hsien Wu, “Integration of SiC into DRAM Cell to Improve Retention Characteristics,” U. S. patent 7015091, 2006/3/21.
Yung-Hsien Wu, “動態隨機存取記憶體及其製造方法,” TW Patent, TW I238495, Date of Patent Grant: 2005/08/21.
Yung-Hsien Wu, “選擇性去除半球狀矽晶粒層的方法及深渠溝電容器之製法,” TW Patent, TW I236053, Date of Patent Grant: 2005/07/11.
Yung-Hsien Wu, Hwei Lin Chuang, “Capacitor Dielectric Layer Structure and Method for Making Same,” China Patent, CN 1630043, Date of Patent Grant: 2007/09/19.
Yung-Hsien Wu, “Method for Selectively Removing Hemispherical Silicon Grain Layer and Making Method for Deep Trench Capacitor,” China Patent, CN 1630063, Date of Patent Grant: 2006/10/18.
巫勇賢, “去除深沟槽结构中半球形晶粒硅层的方法,” China patent CN1624903, 2005/06/08.
Yung-Hsien Wu, “Dual Gate Nitride Process,” US Patent, US 6872664, Date of Patent Grant:2005/03/29.
Yung-Hsien Wu, “Dual Gate Nitride Process,” U. S. patent 6872664, 2005/03/29.
巫勇賢, “移除深溝渠結構中半球形晶粒矽層之方法,” Taiwan patent I227541, 2005/02/01.
Yung-Hsien Wuu and Cheng-Che Lee, “Capacitor Dielectric Structure of a DRAM Cell and Method for Forming Thereof,” U. S. patent 6835630, 2004/12/18.
巫勇賢, “防止阻挡层被过度蚀刻的方法与结构及其应用,” China patent CN1525539, 2004/09/01.
Yung-Hsien Wu, Chia-Lin Ku, “Method for Forming an Oxynitride Layer,” US Patent, US 6764962, Date of Patent Grant: 2004/07/20.
Yung-Hsien Wu and Cheng-Che Lee, “Formation of Capacitor Dielectric Structure, Involves Forming Silicon Nitride Layer on Capacitor Structure on Semiconductor Substrate, Growing Oxide Layer, and Forming Nitridation Layer on Oxide Layer,” German patent DE10250369, 2004/04/29.
巫勇賢, “形成不同厚度氮化層之方法,” Taiwan patent 200436, 2004/04/11.
Yung-Hsien Wu, Cheng-Che Lee, “Manufacturing Method of the Dielectric Layer,” China Patent, CN 1485889, Date of Patent Grant: 2006/04/05.
巫勇賢, 顧家麟, 蕭世崇, 林炳宏, “防止阻障層被過度蝕刻的方法及半導體結構以及應用上述方法形成接觸窗的方法,” Taiwan patent 197740, 2004/02/11.
巫勇賢, 李政哲, “介電層的製作方法,” Taiwan patent 193543 , 2003/12/11.
巫勇賢, 李政哲, “深溝渠電容之介電層的製作方法,” Taiwan patent 183839, 2003/08/01.
Yung-Hsien Wu and Cheng-Che Lee, “Method of Forming A Capacitor Dielectric Structure” U. S. patent 6569731, 2003/05/27.
巫勇賢, 顧家麟, “形成氮氧化層的方法,” Taiwan patent 177607, 2003/04/11.
巫勇賢, 趙宗沛, 顧家麟, “超薄氮化矽薄膜品質監控的方法,” Taiwan patent 159623, 2002/07/01.

Green and Sustainable Electronics Lab

─── PATENTS ───

Cheng-Chieh Lai, Meng-Ting Yu, Yung-Hsien Wu, Kuang-Hsin Chen, “Capacitor Embedded with Nanocrystals,” US Patent, US 10930583, Date of Patent Grant: 2021/02/23. (Invention derived from a collaborative project between TSMC and NTHU led by me)

Cheng-Chieh Lai, Meng-Ting Yu, Yung-Hsien Wu, Kuang-Hsin Chen, “Capacitor Embedded with Nanocrystals,” US Patent, US 10319675, Date of Patent Grant: 2019/06/11 (Invention derived from a collaborative project between TSMC and NTHU led by me)

I-Chen Huang, Kuang-Hsin Chen, Yung-Hsien Wu, Wen-Chao Shen, “Semiconductor Device Structure,” US Patent, US 10163516, Date of Patent Grant: 2018/12/25. (Invention derived from a collaborative project between TSMC and NTHU led by me)

I-Chen Huang, Yi-Ju Hsu, Chi-Wen Liu, Kuang-Hsin Chen, Yung-Hsien Wu, Chin-Yu Chen, “Method of Manufacturing High-K Dielectric Using Hfo/Ti/Hfo Layers,”US Patent, US 10068984, Date of Patent Grant: 2018/09/04. (Invention derived from a collaborative project between TSMC and NTHU led by me)

Cheng-Chieh Lai, Kuang-Hsin Chen, Shih-Kai Fan, Yung-Hsien Wu, Yu-Hsun Chen, “Semiconductor Component and Method for Fabricating the Same,” US Patent, US 10008494, Date of Patent Grant: 2018/06/26. (Invention derived from a collaborative project between TSMC and NTHU led by me)

Cheng-Chieh Lai, Meng-Ting Yu, Yung-Hsien Wu, Kuang-Hsin Chen, “半導體結構與其形成方法,” Taiwan Patent, TW I611551, Date of Patent Grant: 2018/01/11. (Invention derived from a collaborative project between TSMC and NTHU led by me)

Cheng-Chieh Lai, Kuang-Hsin Chen, Shih-Kai Fan, Yung-Hsien Wu, Yu-Hsun Chen, “Semiconductor Component and Method for Fabricating The Same,” Korea Patent, KR 101777020, 2017/09/08. (韓國專利獲證，本人主導之發明，台積電產學合作衍生專利)

賴政杰, 范士凱, 陳光鑫, 巫勇贤, 陳昱勳, “半導體組件及製造其之方法,” Taiwan Patent, I588993, 2017/06/21. (台灣專利獲證，本人主導之發明，台積電產學合作衍生專利)

I-Chen Huang, Kuang-Hsin Chen, Yung-Hsien Wu, Wen-Chao Shen, “Semiconductor Device Structure,” US Patent, US 9673340, 2017/06/06. (美國專利獲證，本人主導之發明，台積電產學合作衍生專利)

Cheng-Chieh Lai, Kuang-Hsin Chen, Shih-Kai Fan, Yung-Hsien Wu, Yu-Hsun Chen, “Semiconductor Component and Method for Fabricating The Same,” US Patent, US 9570568, 2017/02/14. (美國專利獲證，本人主導之發明，台積電產學合作衍生專利)

Yung-Hsien Wu, Min-Lin Wu “單次寫入多次讀取記憶體及其製造方法,” Taiwan Patent, TW I469266, Date of Patent Grant: 2015/01/11.

巫勇賢, 王立康, 荊鳳德, “選擇性射極太陽電池的製程” Taiwan patent I 449198, 2014/08/11.

Yung-Hsien Wu, Li-karn Wang and Feng-Der Chin, “Process for Selective Emitter Solar Cell,” U. S. patent, 8288193, 2012/10/16.

Yung-Hsien Wu, Li-Karn Wang, Feng-Der Chin, “Manufacture Procedure of Selective Emitter Solar Battery” China Patent, CN 102054898B, Date of Patent Grant: 2012/10/31.

Yung-Hsien Wu, “非揮發性記憶體之製造方法,” Taiwan Patent, TW I280668, Date of Patent Grant: 2007/05/01.

Yung-Hsien Wu, “DRAM and Manufacturing Method Thereof,” China Patent, CN 1770427, Date of Patent Grant: 2007/11/21.

Yung-Hsien Wu, “Non-Volatile Memory Manufacturing Method,” China Patent, CN 1767174, Date of Patent Grant: 2007/12/12.

Yung-Hsien Wu, Hwei-Lin Chuang, “電容介電層結構及其製造方法,” Taiwan Patent, TW I254448, Date of Patent Grant: 2006/05/01.

Yung-Hsien Wu and Cheng-Che Lee, “Capacitor Dielectric Structure of a DRAM Cell and Method for Forming Thereof,” US Patent, US 7030441, Date of Patent Grant: 2006/04/18.

Yung-Hsien Wu, “Integration of SiC into DRAM Cell to Improve Retention Characteristics,” U. S. patent 7015091, 2006/3/21.​

Yung-Hsien Wu, “動態隨機存取記憶體及其製造方法,” TW Patent, TW I238495, Date of Patent Grant: 2005/08/21.

Yung-Hsien Wu, “選擇性去除半球狀矽晶粒層的方法及深渠溝電容器之製法,” TW Patent, TW I236053, Date of Patent Grant: 2005/07/11.

Yung-Hsien Wu, Hwei Lin Chuang, “Capacitor Dielectric Layer Structure and Method for Making Same,” China Patent, CN 1630043, Date of Patent Grant: 2007/09/19.

Yung-Hsien Wu, “Method for Selectively Removing Hemispherical Silicon Grain Layer and Making Method for Deep Trench Capacitor,” China Patent, CN 1630063, Date of Patent Grant: 2006/10/18.

巫勇賢, “去除深沟槽结构中半球形晶粒硅层的方法,” China patent CN1624903, 2005/06/08.

Yung-Hsien Wu, “Dual Gate Nitride Process,” US Patent, US 6872664, Date of Patent Grant:2005/03/29.

Yung-Hsien Wu, “Dual Gate Nitride Process,” U. S. patent 6872664, 2005/03/29.

巫勇賢, “移除深溝渠結構中半球形晶粒矽層之方法,” Taiwan patent I227541, 2005/02/01.

Yung-Hsien Wuu and Cheng-Che Lee, “Capacitor Dielectric Structure of a DRAM Cell and Method for Forming Thereof,” U. S. patent 6835630, 2004/12/18.

巫勇賢, “防止阻挡层被过度蚀刻的方法与结构及其应用,” China patent CN1525539, 2004/09/01.

Yung-Hsien Wu, Chia-Lin Ku, “Method for Forming an Oxynitride Layer,” US Patent, US 6764962, Date of Patent Grant: 2004/07/20.

Yung-Hsien Wu and Cheng-Che Lee, “Formation of Capacitor Dielectric Structure, Involves Forming Silicon Nitride Layer on Capacitor Structure on Semiconductor Substrate, Growing Oxide Layer, and Forming Nitridation Layer on Oxide Layer,” German patent DE10250369, 2004/04/29.

巫勇賢, “形成不同厚度氮化層之方法,” Taiwan patent 200436, 2004/04/11.

Yung-Hsien Wu, Cheng-Che Lee, “Manufacturing Method of the Dielectric Layer,” China Patent, CN 1485889, Date of Patent Grant: 2006/04/05.

巫勇賢, 顧家麟, 蕭世崇, 林炳宏, “防止阻障層被過度蝕刻的方法及半導體結構以及應用上述方法形成接觸窗的方法,” Taiwan patent 197740, 2004/02/11.

巫勇賢, 李政哲, “介電層的製作方法,” Taiwan patent 193543 , 2003/12/11.

巫勇賢, 李政哲, “深溝渠電容之介電層的製作方法,” Taiwan patent 183839, 2003/08/01.

Yung-Hsien Wu and Cheng-Che Lee, “Method of Forming A Capacitor Dielectric Structure” U. S. patent 6569731, 2003/05/27.

巫勇賢, 顧家麟, “形成氮氧化層的方法,” Taiwan patent 177607, 2003/04/11.

巫勇賢, 趙宗沛, 顧家麟, “超薄氮化矽薄膜品質監控的方法,” Taiwan patent 159623, 2002/07/01.

Yung-Hsien Wu, “Integration of SiC into DRAM Cell to Improve Retention Characteristics,” U. S. patent 7015091, 2006/3/21.