─── 2018 PAPERS ───
1. Impact of Plasma Treatment on Reliability Performance for HfZrOx-Based Metal-Ferroelectric-Metal Capacitors
Kuen-Yi Chen, Pin-Hsuan Chen, Ruei-Wen Kao, Yan-Xiao Lin and Yung-Hsien Wu*
IEEE Electron Device Lett., vol. 39, no. 1, pp. 87-90, 2018.
2. Enabling Low Contact Resistivity on n-Ge by Implantation after Ti Germanide
Chuan-Pu Chou, Hui-Hsin Chang, and Yung-Hsien Wu*
IEEE Electron Device Lett., vol. 39, no. 1, pp. 91-94, 2018.
3. Direct Fabrication of Inkjet-Printed Dielectric Film for Metal-Insulator-Metal Capacitors
Cheng-Lin Cho, Hsuan-Ling Kao, Yung-Hsien Wu*
Journal of Electronic Materials, vol. 47, no. 1, pp. 677-683, 2018.
4. Implementing P-Channel Junctionless Thin-Film Transistor on Poly-Ge0.95Sn0.05 Film Formed by Amorphous GeSn Deposition and Annealing
Chuan-Pu Chou, Yan-Xiao Lin, and Yung-Hsien Wu*
IEEE Electron Device Lett., vol. 39, no. 8, pp. 1187-1190, 2018.
5. Fully Inkjet-Printed Dual-Mode Ring Bandpass Filter Using a Cross-Bridge Structure Embedded With a Metal–Insulator–Metal Capacitor
Cheng-Lin Cho, Hsuan-Ling Kao, Yung-Hsien Wu*, Hsien-Chin Chiu, and Li-Chun Chang
IEEE Trans. on Components, Packaging and Manufacturing Technology ,vol. 8, no.10, pp. 1869-1875, 2018.
─── 2018 CONFERENCE ───
1. Dependence of Reliability of Ferroelectric HfZrOx on Epitaxial SiGe Film with Various Ge Content
Kuen-Yi Chen, Yen-Hua Huang, Ruei-Wen Kao, Yan-Xiao Lin, and Yung-Hsien Wu*
In Symposium on VLSI Technology, pp. 119-120, Honolulu, USA, 2018.
由國際電機電子工程師學會(Institute of Electrical and Electronics Engineers，IEEE)電子元件學會(Electron Devices Society)與日本應用物理學會(Japan Society of Applied Physics)主辦的Symposium on VLSI Technology是半導體領域最頂尖國際會議之一，被視為積體電路技術與先進半導體元件開發的指標。被接受的論文不僅需要具備學理上的創新，更需要兼具產業價值與前瞻性，與會者包含世界知名大學/研究中心團隊與國際半導體大廠的研究人員。
包括陳坤意同學、黃嬿華同學、高睿彣同學與林彥孝同學在內的研究團隊發現HfZrOx鐵電層在Si晶圓上的可靠度問題如反覆操作下的疲乏(fatigue)效應、印記(imprint)效應以及長時間的狀態保存(retention)劣化效應在SiGe薄膜上均可以獲得改善，且此改善程度隨著Ge濃度增加而越加明顯。當積體電路技術微縮至3 nm後，原有的Si製程平台有機會轉換至SiGe甚至是Ge平台。本研究主要的意義在於以理論及實驗確認未來先進製程轉移至新平台後，鐵電層的品質與可靠度將有更為優異的表現，這對於實現低功率與高速操作的鐵電記憶體與邏輯元件有重要而深遠的影響。
2. Enabling Improved Contact Resistivity for Si, Ge and GeSn Technology
Yung-Hsien Wu*
In Taiwan-Japan Bilateral Seminar-Post Si Era Technology (國家奈米實驗室台日技術論壇), Hsinchu, Taiwan, 2018. (Invited Talk)
3. Enabling Improved Contact Resistivity for Si, Ge and GeSn Technology
Yung-Hsien Wu*, Kuen-Yi Chen, Chuan-Pu Chou and Shih-Chieh Teng
In JSAP Spring Meeting, Tokyo, Japan, 2018. (Invited Talk)
4. Dependence of Capping Layer and Annealing Ambient on Quality of poly-GeSn Film and Performance of p-channel Junctionless Thin Film Transistor
Chuan-Pu Chou, Yan-Xiao Lin, and Yung-Hsien Wu*
In IEEE Silicon Nanoelectronics Workshop, Honolulu, USA, 2018.
