─── 1999-2010 JOURNAL PAPERS ───
1. Improved Electrical Characteristics of CoSi2 Using HF-Vapor Pretreatment
Y. H. Wu, W. J. Chen, S. L. Chang, A. Chin, S. Gwo, and C. Tsai
IEEE Electron Device Lett., vol. 20, no. 5, pp. 200-202, 1999.
2. The Effect of Native Oxide on Epitaxial SiGe from Deposited Amorphous Ge on Si
Y. H. Wu, W. J. Chen, A. Chin, and C. Tsai
Appl. Phys. Lett., vol. 74, no. 4, pp. 528-530, 1999.
3. Gate Oxide Integrity of Thermal Oxide Grown on High Temperature Formed Si0.3Ge0.7
Y. H. Wu and Albert Chin
IEEE Electron Device Lett., vol. 21, no. 3, pp. 113-115, 2000.
4. High Temperature Formed SiGe p-MOSFETs with Good Device Characteristics
Y. H. Wu and Albert Chin
IEEE Electron Device Lett., vol. 21, no. 7, pp. 350-352, 2000.
5. Electrical Characteristics of High Quality La2O3 Gate Dielectric with Equivalent Oxide Thickness of 5Å
Y. H. Wu, M. Y. Yang, Albert Chin, W. J. Chen, and C. M. Kwei
IEEE Electron Device Lett., vol. 21, no. 7, pp. 341-343, 2000.
6. The Fabrication of Very High Resistivity Si with Low Loss and Cross Talk
Y. H. Wu, Albert Chin, K. H. Shih, C. C. Wu, C. P. Liao, S. C. Pai, and C. C. Chi
IEEE Electron Device Lett., vol. 21, no. 9, pp. 442-444, 2000.
7. Thickness Dependent Gate Oxide Quality of Thin Thermal Oxide Grown on High Temperature Formed SiGe
Y. H. Wu, Albert Chin, and W. J. Chen
IEEE Electron Device Lett., vol. 21, no. 6, pp. 289-291, 2000.
8. High Quality Thermal Oxide Grown on High Temperature Formed SiGe
Y. H. Wu, S. B. Chen,and A. Chin
J. Electrochem. Soc., vol. 147, no. 5, pp. 1962-1964, 2000.
9. The Buried Oxide Property in Oxygen Plasma Enhanced Low-Temperature Wafer Bonding
Y. H. Wu, C. H. Huang, W. J. Chen, C. N. Lin, and Albert Chin
J. Electrochem. Soc., vol. 147, no. 7, pp. 2754-2756, 2000.
10. The Effect of Copper on Gate Oxide Integrity
Y. H. Lin, Y. H. Wu, A. Chin, and F. M. Pan
J. Electrochem. Soc., vol. 147, no. 11, pp. 4305-4306, 2000.
11. Boron-Retarded Gate Dielectric Formed by Dry Oxidation of Thermal Nitride
Y. H. Wu, A. Ku,and J. F. Wang
J. Electrochem. Soc., vol. 151, no. 1, pp. F1–F6, 2004.
12. Process Window Enlargement for Borderless Contact Formation by A New BPSG Stack Structure
Y. H. Wu, S. C. Hsiao, P. H. Lin, and C.L. Ku
Electrochemical and Solid-State Lett., vol. 7, no. 1, pp. G1–G4, 2004.
13. Extending Storage Dielectric Scaling Limit by Reoxidizing Nitrided NO Dielectric For Trench DRAM
Y. H. Wu, E. H. , Robert Kuo, Sierra Lai, and C. L. Ku
IEEE Electron Device Lett., vol. 26, no. 2, pp. 66-68, 2005.
14. Improved Electrical Characteristics of NO-Based Storage Dielectric by N2O Wet Oxidation and Postoxidation Treatment for Trench DRAM
Y. H. Wu, C. Y Wang, H. L. Chuang, T. K, Ian Chang, Chia-Ming Kuo, and Alex Ku
Electrochemical and Solid-State Lett., vol. 9, no. 6, pp. G204–G207, 2006.
15. Oxide-Nitride Storage Dielectric Formation in a Single-Furnace Process for Trench DRAM
Y. H. Wu, Ian Chang, C. Y. Wang, Tony Kao, C. M. Kuo, and Alex Ku
IEEE Electron Device Lett., vol. 27, no. 9, pp. 734-736, 2006.
16. High-Performance SrTiO3 MIM Capacitors for Analog Applications
K. C. Chiang, C. C. Huang, G. L. Chen, W. J. Chen, H. L. Kao, Y. H. Wu, Albert Chin, and Sean P. McAlister
IEEE Trans. Electron Devices, vol. 53, no. 9, pp. 2312-2319, 2006.
17. A Method to Monitor the Quality of Ultra-Thin Nitride for Trench DRAM with Buried Strap Structure
Y. H. Wu, C. Y. Wang, Ian Chang, C. K. Kao, C. M. Kuo, and Alex Ku
Semiconductor Science and Technology, vol. 22, no. 2, pp. 49-53, 2007.
18. Thermal gate SiO2 for Ge Metal-Oxide-Semiconductor Capacitors Fabricated on Si Substrate
Y. H. Wu , J. R. Wu, M. L. Wu
Appl. Phys. Lett., vol. 91, p. 093503, 2007.
19. Impact of Organic Contamination from Partially Fluorinated O-Ring in High Temperature Nitride Process on DRAM Performance
Y. H. Wu, C. Y. Wang, C. M. Kuo, and Alex Ku
IEEE Trans. Semiconductor Manufacturing, vol. 21, no. 1, pp. 123-126, 2008.
20. Augmented Cell Performance of NO-Based Storage Dielectric by N2O Treated Nitride Film for Trench DRAM
Y. H. Wu, C. M. Chang, C. Y. Wang, C. K.g Kao, C. M. Kuo, Alex Ku, and Tensor Huang
IEEE Electron Device Lett., vol. 29, no. 2, pp. 149-151, 2008.
21. A Process for In-Line Minority Carrier Lifetime Monitoring for the Furnace Performing Denuded Zone Formation
Y. H. Wu, C. Y. Wang, C. M. Chang, C. K. Kao, C. M. Kuo, and Alex Ku
IEEE Trans. Semiconductor Manufacturing, vol. 21, no. 2, pp. 248-255, 2008.
22. High Density Silicon Nanocrystal Formed on Nitrided Tunnel Oxide for Nonvolatile Memory Application
Y. H. Wu, C. K. Kao, C. Y. Wang, Y. S. Lin, C. M. Chang, C. H. Chuang, C. Y. Lee, C. M. Kuo and Alex Ku
Electrochemical and Solid State Lett., vol. 11, no. 6, pp. H131–H134, 2008.
23. High Density Metal-Insulator-Metal Capacitor Based on ZrO2/Al2O3/ZrO2
Y. H. Wu, C. K. Kao, B. Y. Chen, Y. S. Lin, M. Y. Li and H. C. Wu
Appl. Phys. Lett., vol. 93, p. 033511, 2008.
24. Thermal SiO2 Gated Ge Metal-Oxide-Semiconductor Capacitor on Si Substrate Formed by Thin Amorphous Ge Oxidation and Thermal Annealing
Y. H. Wu, J. R. Wu, Y. S. Lin and M. L. Wu
Appl. Phys. Lett., vol. 93, p. 083506, 2008.
25. Performance-Augmented Storage Capacitor by Reduced Resistance of Polysilicon Electrode for Trench DRAM
Y. H. Wu, C. Y. Wang, C. M. Chang, C. M. Kuo, Alex Ku
Materials Science in Semiconductor Processing, vol. 11, no. 2, pp. 48-52, 2008.
26. Electrical Characteristics of Thermal SiON Gated Ge p-MOSFET Formed on Si Substrate
Y. H. Wu, M. L. Wu, Y. S. Lin, and J. R. Wu
IEEE Electron Device Lett., vol. 30, no. 1, pp. 72-74, 2009.
27. Impact of Preanneal Process on Threshold Voltage of MOS Transistors for Trench DRAM
Y. H. Wu, C. M. Chang, C. Y. Wang, C. K. Kao, C. M. Kuo and Alex Ku
Microelectronics Engineering, vol. 86, no. 1, pp. 33-36, 2009.
28. Nonvolatile Memory with TiN Nanocrystals Three-Dimensionally Embedded in Si3N4 Formed by Spinodal Phase Segregation
Y. H. Wu, L. L. Chen, Y. S. Lin, C. H. Chang, J. H. Huang, and G. P. Yu
IEEE Electron Device Lett., vol. 30, no. 6, pp. 617-619, 2009.
29. Metal-Insulator-Metal Capacitor with High Capacitance Density and Low Leakage Current using ZrTiO4 Film
Y. H. Wu, L. L. Chen, B. Y. Chen, J. R. Wu, and M. L. Wu
Appl. Phys. Lett., vol. 95, p. 113502, 2009.
30. Ge-based Silicon-Oxide-Nitride-Oxide-Silicon-Type Nonvolatile Memory Formed on Si Substrate
Y. H. Wu, J. R. Wu , M. L. Wu , L. L. Chen , Y. S. Lin
J. Electrochem. Soc., vol. 156, no. 12, pp. H944-H947, 2009.
31. Nitrided Tetragonal ZrO2 as the Charge-Trapping Layer for Nonvolatile Memory Application
Y. H. Wu, L. L. Chen, Y. S. Lin, M. Y. Li and H. C. Wu
IEEE Electron Device Lett., vol. 30, no. 12, pp. 1290-1292, 2009.
32. Selective Emitter Solar Cell Formation by NH3 Plasma Nitridation and Single Diffusion
Y. H. Wu, L. L. Chen, J. R. Wu, and M. L. Wu
Semiconductor Science and Technology, vol. 25, no. 1, pp. 015001, 2010.
33. Selective Emitter Solar Cell Formation by NH3 Plasma Nitridation and Single Diffusion
Y. H. Wu, L. L. Chen, J. R. Wu, and M. L. Wu
Semiconductor Science and Technology, vol. 25, no. 1, pp. 015001, 2010.
34. Impact of Top Electrode on Electrical Stress Reliability of Metal-Insulator-Metal Capacitor With Amorphous ZrTiO4 Film
Y. H. Wu, C. C. Lin, L. L. Chen, B. Y. Chen, M. L. Wu, and J. R. Wu
Appl. Phys. Lett., vol. 96, p. 133501, 2010.
35. Structure and Property Changes of ZrO2/Al2O3/ZrO2 Laminate Induced by Low-Temperature NH3 Annealing Applicable To Metal-Insulator-Metal Capacitor
Y. H. Wu, M. Y. Li, B. S. Tsai, P. C. Jiang, H. C. Wu, Y. J. Lin
Thin Solid Films, vol. 518, no. 18, pp. 5272-5277, 2010.
36. Electrical Characteristics of Ge MOS Device on Si Substrate With Thermal SiON as Gate Dielectric
Y. H. Wu, M. L. Wu, J. R. Wu, and Y. S. Lin
Microelectronics Engineering, vol. 87, no. 11, pp. 2423-2428, 2010.
37. Ge-stabilized Tetragonal ZrO2 as Gate Dielectric for Ge MOS Capacitors Fabricated on Si Substrate
Y. H. Wu, M. L. Wu, J. R. Wu, and L. L. Chen
Appl. Phys. Lett., vol. 97, p. 043503, 2010.
38. Tetragonal ZrO2/Al2O3 Stack as High-κ Gate Dielectric for Si-Based MOS Devices
Y. H. Wu, L. L. Chen, R. J. Lyu, M. Y. Li and H. C. Wu
IEEE Electron Device Lett., vol. 31, no. 9, pp. 1014-1016, 2010.
39. (ZrO2)x(La2O3)1-x Alloy as High-k Gate Dielectric for Advanced CMOS Devices
Y. H. Wu , L. L. Chen, C. Y. Hou, J. R. Wu, M. L. Wu, and R. J. Lyu
ECS Trans., vol. 33, 2010.
40. Nonvolatile Memory With Nitrogen-Stabilized Cubic Phase ZrO2 as Charge Trapping Layer
Y. H. Wu, L. L. Chen, J. R. Wu, M. L. Wu, C. C. Lin and C. H. Chang
IEEE Electron Device Lett., vol. 31, no. 9, pp. 1008-1010, 2010.
─── 1999-2010 CONFERENCE PAPERS ───
1. Electrical and Structure Characterization of Single Crystalline SiGe Formed by Ge Deposition and RTP
Y. H. Wu, W. J. Chen, A. Chin, and C. Tsai
The 41st TMS Electronic Materials Conference (EMC) Dig., 1999.
2. High Quality La2O3 and Al2O3 Gate Dielectrics with Equivalent Oxide Thickness 5-10Å
Albert Chin, Y. H. Wu, S. B. Chen, C. C. Liao, and W. J. Chen
Symp. on VLSI Tech., pp. 16-17, 2000.
3. The Performance Limiting Factors as RF MOSFETs Scaling Down
Y. H. Wu, Albert Chin, C. S. Liang, and C. C. Wu
IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, pp. 151-154, 2000.
4. RF Loss and Cross Talk on Extremely High Resistivity (10k-1m Ohm-cm) Si Fabricated by Ion Implantation
Y. H. Wu, Albert Chin, K. H. Shih, C. C. Wu, C. P. Liao, S. C. Pai, and C. C. Chi
IEEE International Microwave Symposium, pp.221-224, 2000.
5. Improved Shallow Junction Integrity Using Single Crystalline CoSi2
Y. H. Wu, K. T. Chan, S. B. Chen, W. J. Chen, and Albert Chin
The 42nd TMS Electronic Materials Conference (EMC) Dig., 2000.
6. High Quality Thermal Ultra-Thin Gate Oxide Directly Grown on High Temperature Formed Si0.3Ge0.7
S. B. Chen, C. H. Huang, Y. H. Wu, W. J. Chen, and Albert Chin
The 42nd TMS Electronic Materials Conference (EMC) Dig., 2000.
7. High Frequency Characterization of Mega-Ohm Resistivity Si Formed by High-Energy Ion Implantation
Y. H. Wu, M. Y. Yang, S. B. Chen, W. J. Chen, Albert Chin, and C. M. Kwei
The 42nd TMS Electronic Materials Conference (EMC) Dig., 2000.
8. Gate Dielectric Formed by Dry Oxidation of Thermal Nitride and Its Capability to Prevent Boron Penetration
Y. H. Wu, Alex Ku, J. F. Wang
The 44th TMS Electronic Materials Conference (EMC) Dig., 2002.
9. The Modeling of Temperature Distribution on Vertical LPCVD Furnace for Depositing Film on Deep Trench Pattern Wafer
C. Y. Wang, Y. H. Wu, C. L. Ku
The 20th VLSI Multilevel Interconnection Conference (VMIC) Dig., 2003.
10. The Effect of In-Situ Liner Oxide on Threshold Voltage and Its Application to Enhance Yield Stability
Y. H. Wu, C. Y. Wang, W. H. Hsieh, P. Y. Chang, and C. L. Ku
The 21st VLSI Multilevel Interconnection Conference (VMIC) Dig., 2004.
11. Increasing of Arsenic Diffusion into Silicon From Arsenic-Doped Oxide Source on Deep Trench Based Capacitor DRAM
C. Y. Wang, Y. H. Wu, C. L. Ku
The 21st VLSI Multilevel Interconnection Conference (VMIC) Dig., 2004.
12. Very Low Voltage and High Speed MONOS Nonvolatile Memory
A. Chin, C. H. Lai, K. C. Chiang, W. J. Chen, Y. H. Wu, and H. L. Hwang
The 7th International Conference on Solid-State and Integrated-Circuit Technology (ICSICT), 2006.
13. Resistance Reduction of n+ Poly-Silicon Fill for Storage Capacitance in Trench DRAM
C. Y. Wang, Y. H. Wu, C. Y. Teng, C. K. Kao, C. M. Kuo, Alex Ku, Tensor Huang
The 211th Meeting of The Electrochemical Society (ECS) Dig., 2007.
14. Improved Cell Performance of NO-Based Storage Dielectric by N2O Treated Nitride Film for Trench DRAM
C. M. Chang, Y. H. Wu, C. K. Kao, C. Y. Wang, C. M. Kuo, Alex Ku, and Tensor Huang
The 49th TMS Electronic Materials Conference (EMC) Dig., 2007.
15. Nonvolatile Memory with High Density Silicon Nanocrystal Formed on Nitrided Tunnel Oxide
Y. H. Wu, C. Y. Wang, C. K. Kao, C. M. Chang, Y. S. Lin, C. Y. Lee, C. H. Chuang, C. M. Kuo and Alex Ku
International Conference on Nanoscience and Nanotechnology (ICONN), Melbourne, Australia, 2008.
16. High-Performance MIM Capacitor Using ZrO2/Al2O3/ZrO2 Dielectric
Bo-Yu Chen, Yuan-Sheng Lin, Yung-Hsien Wu, Chien-Kang Kao, Ming-Yen Li and Hsiao-Che Wu
The 214th Meeting of The Electrochemical Society (ECS) Dig., 2008.
17. Electrical Characteristics of Ge p-MOSFETs Formed on Si Substrate with Thermal SiON as Gate Dielectric
Yung-Hsien Wu, Min-Lin Wu, Jia-Rong Wu and Yuan-Sheng Lin
International Conference on Solid State Devices and Materials (SSDM), Tsukuba, Japan, 2008.
18. Hybrid TiN Nanocrystals/Si3N4 Nonvolatile Memory Featuring Low Voltage Operation by Spinodal Phase Segregation
Lun-Lun Chen, Chia-Hsuan Chang, Yuan-Sheng Lin and Yung-Hsien Wu
Device Research Conference, Penn State University, USA, 2009.
19. Ge Nanocrystals Embedded in SiON as the Hybrid Charge Trapping Layer for Nonvolatile Memory Application
Min-Lin Wu, Jia-Rong Wu, Lun-Lun Chen, and Yung-Hsien Wu
Conference on Nano and Giga Challenges in Electronics, Photonics and Renewable Energy, Hamiltion, Canada, 2009.
20. Nonvolatile Memory with Nitrided Tetragonal ZrO2 as Charge- Trapping Layer
Lun-Lun Chen, Min-Lin Wu, Jia-Rong Wu, Yung-Hsien Wu, Ming-Yen Li, and Hsiao-Che Wu
Conference on Nano and Giga Challenges in Electronics, Photonics and Renewable Energy, Hamiltion, Canada, 2009.
21. SONOS-Type Nonvolatile Memory Fabricated on Thin Epitaxial Ge on Si Substrate
Jia-Rong Wu, Lun-Lun Chen, Min-Lin Wu, and Yung-Hsien Wu
Conference on Nano and Giga Challenges in Electronics, Photonics and Renewable Energy, Hamiltion, Canada, 2009.
22. SONOS-Type Nonvolatile Memory Formed on Epitaxial-Ge Layer on Si Substrate
Jia-Rong Wu, Min-Lin Wu, Lun-Lun Chen, Yuan-Sheng Lin, and Yung-Hsien Wu
International Conference on Solid State Devices and Materials (SSDM), Miyagi, Japan, 2009.
23. Nonvolatile Memory with Nitrided Tetragonal ZrO2 as Charge-Trapping Layer
Lun-Lun Chen, Yuan-Sheng Lin, Yung-Hsien Wu, Ming-Yen Li and Hsiao-Che Wu
International Electron Devices and Materials Symposia (IEDMS), Taiwan, 2009.
24. MIM Capacitors with ZrTiO4 as Insulator Featuring High Capacitance Density and Low Leakage Current
Chia-Chun Lin, Bo-Yu Chen, Lun-Lun Chen, Min-Lin Wu, Jia-Rong Wu and Yung-Hsien Wu
IEEE International NanoElectronics Conference (INEC), Hong-Kong, 2010.
25. Cubic ZrO2 as Charge-Trapping Layer for Nonvolatile Memory Application
Yao-Chung Hu, Lun-Lun Chen, Jia-Rong Wu, Min-Lin Wu, Chia-Hsuan Chang, and Yung-Hsien Wu
in The 217th Meeting of The Electrochemical Society (ECS) Dig., Vancouver, Canada, 2010.
26. Tetragonal ZrO2-Gated Ge MOS Capacitors Fabricated on Si Substrate
Min-Lin Wu, Lun-Lun Chen, Jia-Rong Wu, and Yung-Hsien Wu
in The 217th Meeting of The Electrochemical Society (ECS) Dig., Vancouver, Canada, 2010.
27. Metal-Gate/High-κ CMOS Scaling from Si to Ge at Small EOT
A. Chin, W. B. Chen B. S. Shie, K. C. Hsu, P. C. Chen, C. H. Cheng, C. C. Chi, Y. H. Wu, K. S. Chaing-Liao, S. J. Wang, C. H. Kuan, and F. S. Yeh
in The 10th Int’l Conf. on Solid-State and Integrated-Circuit Technology (ICSICT), 2010.
28. (ZrO2)x(La2O3)1-x Alloy as High-k Gate Dielectric for Advanced CMOS Devices
Chin-Yao Hou, Lun-Lun Chen, Jia-Rong Wu, Min-Lin Wu, Rong-Jhe Lyu and Yung-Hsien Wu
in The 218th Meeting of The Electrochemical Society (ECS) Dig., Las Vegas, USA, 2010.
29. MIM Capacitors With Stacked TiO2/Y2O3 Insulator Featuring High Capacitance Density and Low Leakage Current
Chia-Chun Lin, Yao-Chung Hu, Lun-Lun Chen, Min-Lin Wu, Jia-Rong Wu and Yung-Hsien Wu
in International Conference on Solid State Devices and Materials (SSDM), Tokyo, Japan, 2010.
30. Al2O3/Nitrided Tetragonal ZrO2 as Advanced Gate Stack
Lun-Lun Chen, Rong-Jhe Lyu, Yung-Hsien Wu, Ming-Yen Li and Hsiao-Che Wu
in International Electron Devices and Materials Symposia (IEDMS), Taiwan, 2010.
31. MIM Capacitors With Ge-Stabilized Tetragonal ZrO2/La-Doped ZrO2 Dielectric Featuring High Capacitance and Low Leakage Current
Chia-Chun Lin, Yao-Chung Hu, Wei Yuan Ou, Lun-Lun Chen, Jia-Rong Wu, Min-Lin Wu and Yung-Hsien Wu
in International Electron Devices and Materials Symposia (IEDMS), Taiwan, 2010.